1. Field of the Invention
This invention relates to a semiconductor device wherein a high speed vertical type bipolar transistor and high voltage vertical type bipolar transistor are formed on the same substrate and a method of making the same.
2. Description of the Related Art
A vertical type NPN bipolar transistor of the related art constructed as a high speed bipolar transistor and a vertical type NPN bipolar transistor of the related art constructed as a high voltage bipolar transistor will be described with reference to FIG. 1 and FIG. 2.
FIG. 1 is a schematic sectional view of the construction of a high speed bipolar transistor.
As shown in FIG. 1, an N-type epitaxial layer 12 is formed on a P-type silicon substrate 11. An N+-type embedded diffusion layer 31 is formed in an upper part of the P-type silicon substrate 11, and this N+-type embedded diffusion layer 31 is also diffused into a lower part of the epitaxial layer 12. Also, on the epitaxial layer 12 is formed a device separating oxide film 13 for isolating a region where a high speed bipolar transistor 1 is formed. Below this device separating oxide film 13 a P+-type device separating diffusion layer 14 reaching the silicon substrate 11 is formed.
A P-type base layer 32 and a P+-type graft base layer 33 connecting with this base layer 32 are formed in an upper part of the epitaxial layer 12 in the region where the high speed bipolar transistor 1 is formed. An N+-type emitter layer 34 is formed in an upper part of this base layer 32. Also, an N+-type collector leading layer 35 connecting with the embedded diffusion layer 31 is formed in a position away from the graft base layer 33 in the epitaxial layer 12 in the region where the high speed bipolar transistor 1 is formed.
A first oxide film 15 is formed on the epitaxial layer 12, and a first opening 16 is formed in the first oxide film 15 above the graft base layer 33. A base leading electrode 36 connecting with the graft base layer 33 through the first opening 16 is formed on the first oxide film 15. Also, a second oxide film 17 is formed on the first oxide film 15 in such a state that it covers the base leading electrode 36.
A second opening 18 is formed in the second oxide film 17 above the base layer 32, and on the side wall thereof a side wall insulating film 19 is formed. The inner side of this side wall insulating film 19 forms an emitter opening, and the above-mentioned emitter layer 34 is at the bottom of this emitter opening.
An emitter leading electrode 37 connecting with the emitter layer 34 through the emitter opening is formed on the second oxide film 17.
Also formed are a base electrode 38 connecting with the base leading electrode 36 through the second oxide film 17, an emitter electrode 39 connecting with the emitter leading electrode 37, and a collector electrode 40 connecting with the collector leading layer 35 through the second oxide film 17 and the first oxide film 15.
Thus is constructed the high speed bipolar transistor 1.
FIG. 2 is a schematic sectional view of the construction of a high voltage bipolar transistor.
As shown in FIG. 2, an N-type epitaxial layer 50 thicker than the epitaxial layer (12) of the high speed bipolar transistor (1) described above is formed on a P-type silicon substrate 11. An N+-type embedded diffusion layer 51 deeper than the embedded diffusion layer (31) of the high speed bipolar transistor (1) described above is formed in an upper part of the silicon substrate 11, and this embedded diffusion layer 51 is also diffused into a lower part of the epitaxial layer 50. Also, on the epitaxial layer 50 is formed a device separating oxide film 13 for isolating a region where a high voltage bipolar transistor 2 is formed. Below this device separating oxide film 13 a P+-type device separating diffusion layer 14 reaching the silicon substrate 11 is formed.
A P-type base layer 52 and a P+-type graft base layer 53 connecting with this base layer 52 are formed in an upper part of the epitaxial layer 50 in the region where the high voltage bipolar transistor 2 is formed. An N+-type emitter layer 54 is formed in an upper part of this base layer 52. Also, an N+-type collector leading layer 55 connecting with the embedded diffusion layer 51 is formed in the epitaxial layer 50 in a position away from the graft base layer 53 in the region where the high voltage bipolar transistor 2 is formed.
A first oxide film 15 is formed on the epitaxial layer 50, and a first opening 16 is formed in the first oxide film 15 above the graft base layer 53. A base leading electrode 56 connecting with the graft base layer 53 through the first opening 16 is formed on the first oxide film 15. Also, a second oxide film 17 is formed on the first oxide film 15 in such a state that it covers the base leading electrode 56.
A second opening 18 is formed in the second oxide film 17 above the base layer 52, and on the side wall thereof a side wall insulating film 19 is formed. The inner side of this side wall insulating film 19 forms an emitter opening, and the above-mentioned emitter layer 54 is at the bottom of this emitter opening.
An emitter leading electrode 57 connecting with the emitter layer 54 through the emitter opening is formed on the second oxide film 17.
Also formed are a base electrode 58 connecting with the base leading electrode 56 through the second oxide film 17, an emitter electrode 59 connecting with the emitter leading electrode 57, and a collector electrode 60 connecting with the collector leading layer 55 through the second oxide film 17 and the first oxide film 15.
Thus is constructed the high voltage bipolar transistor 2.
The impurity distributions of the high speed bipolar transistor 1 and the high voltage bipolar transistor 2 described above will now be explained with reference to FIG. 3 and FIG. 4.
FIG. 3 shows the impurity distribution in the depth direction of the high speed bipolar transistor 1. In FIG. 3, the vertical axis shows impurity concentration on a log scale and the horizontal axis shows depth from the surface of the silicon substrate.
As shown in FIG. 3, the impurity distribution in the depth direction of the high speed bipolar transistor 1 has the characteristic that the N-type epitaxial layer 12 is thin and its impurity concentration is high.
FIG. 4 shows the impurity distribution of the high voltage bipolar transistor 2. In FIG. 4 also, the vertical axis shows impurity concentration on a log scale and the horizontal axis shows depth from the surface of the silicon substrate.
As shown in FIG. 4, in the impurity distribution of the high voltage bipolar transistor 2, the impurity concentrations of the N+-type emitter layer 54 and the P-type silicon substrate 11 are the same as the impurity concentrations of their counterparts in the high speed bipolar transistor 1. On the other hand, there is the characteristic that the N-type epitaxial layer 50, compared to the N-type epitaxial layer 12 of the high speed bipolar transistor 1, is thick and its impurity concentration is low. Also, the P-type base layer 52 generally is thicker than the base layer of a high speed bipolar transistor.
Generally, to make the breakdown voltage of the kind of bipolar transistor described above high, it is necessary to make the concentration of the N-type epitaxial layer low and make the layer thick.
The lower the impurity density of the epitaxial layer is, and the thicker the epitaxial layer is, the greater the voltage (breakdown voltage) of the bipolar transistor is. Also, even if the density of the epitaxial layer is kept fixed and only the thickness of the epitaxial layer is increased, the voltage (breakdown voltage) of the bipolar transistor rises.
The relationship between the base impurity density and the base width is such that to increase the breakdown voltage of a bipolar transistor it is necessary to moderately increase the base concentration and to some extent make the base width thick.
For this reason also, it is necessary to make the N-type epitaxial layer thick.
When the concentration of the N-type epitaxial layer is made low and the layer is made thick, it is necessary to make the N+-type embedded layer region for suppressing parasitic bipolar transistor operation wide and make the P+ separating region deep in order to certainly effect device separation. That is, it is necessary to make the cell dimensions large.
However, in a high speed bipolar transistor, to suppress the collector Kirk effect, it is necessary to make the concentration of the N-type epitaxial layer high and make the layer thin. On the other hand, as explained above, in a high voltage bipolar transistor, to obtain voltage, it is necessary to make the concentration of the N-type epitaxial layer low and make the layer thick.
Thus, the epitaxial layer requirements of a high speed bipolar transistor and a high voltage bipolar transistor have been conflicting ones. Consequently, it has been difficult to form a high speed bipolar transistor and a high voltage bipolar transistor on the same substrate.